1. Field of the Invention
The present invention relates to a method of fabricating a transistor in a semiconductor substrate, and more particularly, to a method of fabricating a CMOS (complementary metal oxide semiconductor) transistor.
2. Discussion of the Related Art
Generally, a transistor, such as a metal oxide semiconductor (MOS) transistor, which is constructed with a gate electrode, a source, and a drain, is essential to operating a semiconductor device.
FIG. 1 is a flowchart of a method of fabricating a CMOS transistor according to a related art.
Referring to FIG. 1, a device isolation layer is formed on a semiconductor substrate to define an active area and a field area (S1). The device isolation layer is called a field oxide layer and is formed by LOCOS (local oxidation of silicon) or STI (shallow trench isolation).
A well is formed in the substrate for forming a CMOS transistor therein (S2). An n-well is formed for a PMOS transistor and a p-well is formed for an NMOS transistor.
A gate oxide layer and a polysilicon layer are formed on the substrate in turn to form a gate electrode.
The polysilicon layer is etched to form a polysilicon gate using a mask pattern (S3).
In etching the polysilicon layer using a gate mask pattern, the gate oxide layer is degraded. In order to compensate for the degradation of the gate oxide layer and to protect the substrate against LDD (lightly doped drain) ion implantation, gate sidewall oxidation, i.e., re-oxidation is carried out to form a screen oxide layer on an exposed surface of the substrate and a sidewall of the gate. In doing so, the screen oxide layer is formed to be 15˜30 Å thick.
Subsequently, oxidation annealing is carried out for hardening the screen oxide layer (S4). In doing so, annealing is performed at 1,000° C. (or higher) for 10 seconds in an atmosphere of N2 gas.
In order to prevent hot carriers from being generated from a drain edge of an NMOS transistor by a high electric field for example, ion implantation is carried out on the substrate to form LDD regions aligned with the gate (S5).
Subsequently, a spacer is formed on a sidewall of the polysilicon gate (S6). In doing so, the spacer has an N—O—N structure including a spacer nitride layer/buffer oxide layer/sealing nitride layer.
And, source/drain regions extending from the LDD are formed by ion implantation to be aligned with the spacer in the substrate (S7).
Finally, silicidation is carried out on the substrate to lower contact resistance of the source/drain regions to complete the fabrication of the transistor (S8).
As mentioned in the foregoing explanation, the screen oxide layer is formed by sidewall oxidation of the polysilicon gate to serve as a screen against LDD ion implantation and to suppress leakage current.